When creating a new integrated circuit, the initial focus is naturally on the design. When it comes to tapeout, then fabrication, multiproject wafer (MPW) services are growing in popularity as deep-submicron technologies become the norm and as both mask and wafer fabrication costs soar. However, device packaging is often overlooked until the end of the process. That may be because some fabs and MPW providers have relatively little to offer with respect to packaging, or it may be simply that designers see packaging as the last thing they need to worry about.
In fact, choosing the right package both during the creation of a chip for the test phase of development and for the final device can not only reduce your time-to-market, but also help you create tangible benefits for your customers.
The choice of packages has never been greater, and some MPW providers now recognize the importance of providing chip developers with optimized packages throughout the development of silicon devices. Most frequently, this is done through partnering with established packaging specialists. Let’s take a look at some of the available options and what they have to offer.
|System-in-package combines IC, discrete and passive parts within a single custom or standard-outline SIP
Open-cavity packages are ideal for focused-ion-beam (FIB) analysis and for probing silicon devices during development. Being able to carry out such tests directly on the die is an important factor in speeding design work and ensuring device integrity before moving to volume production. Until relatively recently, however, such packages were usually large ceramic types. These are expensive, and high-speed signal integrity cannot be evaluated accurately, because package interconnects are not the same as those in the final package.
Recent developments have changed all that, and open-cavity packages are now available in several popular formats, including QFN/MLP, QFP and SOIC/SSP. These premolded packages meet the latest Jedec outline and footprint standards. Their copper lead frames are gold-plated to military standards, so they are mechanically stable and have electrical characteristics very similar to fully encapsulated, molded types that would be used in volume production. Typical package sizes range from 3 x 3 mm to 10 x 10 mm.
Chip-scale packaging (CSP) is increasingly popular because of its relatively low cost, small size and high performance. It provides protection for the die surface, minimizes stress between the printed-circuit board and the die, and facilitates changes in interconnect arrangements between the die and pc board. High-speed signal performance is particularly good because interconnects are kept very short. Rather than the conventional process of wafer fabrication, dicing and packaging, the creation of wafer-level chip-scale packages involves packaging complete wafers and then dicing them.
Creating a CSP involves covering the wafer with a layer of passivation (polyimide), then etching vias down to the bond pads–traditionally located around the outside of each device–and filling the vias with conductive material. A copper retracing layer is then deposited, connecting to the top of the vias and forming a matrix pattern across the whole chip. Solder bumping–creating the balls that will contact the board–is achieved by depositing a thick layer of passivation, etching vias into this at the desired connection points, then filling the vias with solder. The top layer of passivation is then removed, and surface tension makes the columns of solder form into ball shapes.
Highest performance is achieved by keeping critical signals on the outside of the device so they have the shortest connections to the die. CSP also offers good thermal performance; heat is easily dissipated because there is no insulating packaging surrounding the die.
Where space in the X-Y plane is at a premium, stacked-die packaging allows for very efficient use of motherboard real estate, reducing size, weight and system cost. Taking the MPW route with stacked-die packaging can allow complex systems to be prototyped earlier than waiting for a single IC to be developed. Using stacked dice can therefore be a good way to prove that a design meets the required specification, on the way to moving everything onto a single process. For example, flash memory, digital and analog elements of a design can be produced on different dice but housed in the same package.
The technology also enables the flexibility of combining custom chips with off-the-shelf devices to reduce system cost. Dice are tested before being put into the stacks to ensure that only known-good dice (KGD) are used.
Three approaches can be taken to stacked-die construction: same-die stacks, pyramid stacks and overhand cross stacks.
When two dice are used, the maximum package height will typically be in the region of 1.4 mm. It is also possible to stack three or more dice in a single package when board space is limited but a little more height is available.
The most common applications for stacked-die packages are in portable electronic devices such as cell phones, PDAs and other wireless consumer systems.
The system-in-package (SIP) approach is becoming increasingly popular not only for its very high density but because as passive component sizes shrink, the devices become more difficult and expensive to handle. Ceramic capacitors that measure 1 x 0.5 mm are now common, and devices down to 0.4 x 0.2 mm are available in values up to 1000 pF at 6.3 Vdc.
However, the cost of capital equipment to handle such tiny parts can make it difficult to find an economical way to take advantage of the available miniaturization.
The SIP approach combines multiple ICs, discrete semiconductors and passive components onto a single package, providing a complete functional system in one module that can be processed much like a standard component during board assembly. Unlike system-on-chip (SoC) designs, which employ a singe die, SIP designs are integrated by stacking or placing chips and components on a substrate, typically a BGA laminate or QFP lead frame.
SIP has performance and size advantages over component-level designs. In digital circuits, it can provide better memory bandwidth than SoC-based designs. And in analog and mixed-signal designs, the proximity of passive and active parts minimizes stray capacitance and unwanted inductance to optimize high-speed signal performance.
About the author
Wes Hansford (hansford@ mosis.com) is deputy director of Mosis. He has 25 years’ experience working in the semiconductor industry in technical and management roles. He holds an MSEE degree from the University of Southern California.